In conventional memory systems, such as a Random Access Memory (RAM) memory cells are accessed by a processor that specifies a storage address that is associated with the given set of memory cells. This system provides rapid access to any portion of the memory system within certain limitations.
In associative memory systems, such as Content Addressable Memory (CAM), the system has the ability to perform a search and compare operation based on the contents of its memory cells, such that a storage address is retrieved by simultaneously searching all memory cells for a particular bit sequence. In other words user-specified data in a comparand register is compared directly with all the stored data held in the CAM's address space simultaneously. The CAM then generates a match or mismatch result, the former including an address of the memory cells at which the match occurred.
When storage requirements exceed the number of entries that may be stored on a single CAM device, multiple devices can be cascaded together to expand the number of search entries. This can be achieved, by employing well known methods for connecting a plurality of CAMs, such as daisy chain or multi-drop cascading methods. The cascaded devices may then be searched as a single entity.
In using these well-known methods, a plurality of CAMs are connected to a host controller. However, because search data must be applied to all CAMs in the cascade, long interconnects, typically arising from use of common forwarding buses, between the host controller and the cascade of CAMs introduce delay into the propagated signals. As the number of CAMs connected to a common forwarding bus from a host controller is increased, latency time for signals propagated on the bus becomes longer due to increased load capacitance and resistance. Thus the overall speed of the cascaded CAM structure is limited. These long interconnect delay problems become especially pronounced as individual CAMs capable of operating at high clock speeds, typically 75 MHz or faster, are becoming available.
Also, like in single CAM devices, multiple matches can exist in a cascaded CAM system, and accordingly a priority determining mechanism must be employed to resolve multiple match instances in a cascade arrangement.
A need therefore exists for an improved method and system for cascading a plurality of CAMs which reduces the delay time for signals propagated along the forwarding bus.